Conventional computing systems rely on static combinations of logic gates to implement one or more predefined Boolean algebraic functions and/or memory. Within static computing systems, the various hardware components of the computing system cannot be reconnected or reconfigured during operation. For example, the functionality of hardware components such as logic gates or memory latch cannot be dynamically changed once the component is fabricated.
Recently, a new paradigm in application specific integrated circuit (IC) design has begun to emerge. Due to the high cost of IC design and fabrication, companies have looked for ways to avoid the majority of IC fabrication costs by utilizing hardware that is electrically or metal/via programmed. The electrical example is the FPGA. Both logical programming and interconnect programming are possible by way of externally applied electrical programming signals. This methodology allows a single IC to be used for any reasonable logic requirement. The silicon is fixed and since it is used for multiple applications and customers, the cost is spread across all of these platforms and the high non-recurring expense (NRE) associated with full custom solutions is avoided (this could be well over multi-millions of dollars for 65 and 45 nm IC technology). An issue with FPGA technology is that to support any application, the overhead required for flexible logic and interconnect is extremely high. This may amount to 80-90% of the total die area.
All field-programmable circuit elements or cells are fixed in size and structure. All cells or fixed configurable logic element (CLE) of a FPGA are not utilized. This unused circuitry is inefficient, for both simple and complex functions. Moreover, there may be large amounts of the array simply not utilized because the total logic requirement is well below the array capability. These issues may not be problematic if designs have a low run rate in manufacturing, but if millions of pieces are required then customers lose margin by paying for silicon not utilized.
An alternative to classic Boolean logic circuits has been developed based on chaotic or non-linear elements known as Chua's circuit. This implements classic chaos theory behavior. The Chua circuit was first introduced in the early 1980s by Leon O. Chua, its ease of construction has made it a ubiquitous real-world example of a chaotic system.
Chua's circuit, although easy to implement with off the shelf discrete components, is not feasible to manufacture using integrated circuit technology because the necessary inductors and capacitors consume too much circuit area and the large number of operational amplifiers necessitate numerous transistors. Moreover, integrated circuits based on Chua's circuit, are often very difficult to control because the component values are very sensitive. Even a minor change to the component values often times cause chaotic oscillations to damp out.